RAMP - Research Accelerator for Multiple Processors

Research Accelerator for Multiple Processors

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	RAMP Sites

	Getting Started Infrastructure Repository Mar08 ASPLOS Jan08 Retreat Mar07 Bootcamp Jan07 Retreat Aug06 Workshop Jan06 Workshop Open System Repository


	Related Research

	ATLAS BEE2 Project BEE Projects ParLab ProtoFlex RAMP Gold


	Sponsors

	This material is based upon work supported by the National Science Foundation under Grant No. 0551739


	UC Berkeley

	EECS Department CS61C Course Site CS150 Course Site CS152 Course Site

News

RAMP Wrap Up Agenda

[8-25-2010]

Time	Speaker	Title
8:30:00	Breakfast
9:00:00	John Wawrzynek	Intros
9:15:00	David Patterson	RAMP Retrospective
10:00:00	Derek Chiou	FPGA Accelerated Simulation Technologies - FAST
10:25:00	Christos Kozyrakis	Using FPGAs for Systems Research: Successes, Failures, and Lessons
10:50:00	Break
11:20:00	James Hoe	RAMP-Tartan Wrap
11:45:00	Michael Adler	HASim
12:10:00	Krste Asanovic	RAMP Gold/Midas
12:35:00	Lunch
14:00:00	Chuck Thacker	RAMPing Down
15:00:00	Kees Vissers	RAMP Wrap
15:45:00	Break
16:15:00	Mike Butts	Logic Emulation and Prototyping
17:00:00	Kathy Yelick	RAMP for Exascale
17:45:00	Krste Asanovic	RAMP For Gold Wrap
18:00:00	Posters/Demos
19:00:00	Dinner
20:30:00	End


	High Scale Network Research	[4-9-2010]

	There's an interesting post on James Hamilton's blog about High Scale Network Research which discusses RAMP Gold and the Internet in a Box project that uses it.


	BEE3 Embedded Controller	[2-23-2010]

	As announced at the Winter 2010 retreat at Santa Cruz, BWRC has under development an embedded controller for the BEE3 platform for an allied project. The unit can extend the capability of the RAMP hardware, and will tentatively be retrofitted as an upgrade upon completion during 1H 2010. Technical details are in the public domain, and will be posted when the design is finalized. For more information contact Dan Burke through the BWRC website.


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