RAMP - Jan 2006 Workshop

Jan 2006 Workshop

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	This material is based upon work supported by the National Science Foundation under Grant No. 0551739


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	Info

	This is a combined RAMP & BEE2 Workshop, held January 17-19, 2006 in 125 Cory Hall at UC Berkeley. Attendance by invitation (academic researchers) only. The RAMP/BEE2 workshop is a by-invitation only event for hands-on experience using Xilinx XUP boards and the BEE2 system, with special emphasis on the use of these systems within the RAMP project. The workshop will be held in 125 Cory Hall, UC Berkeley, Tuesday through Thursday, January 17-19, 2006. All day Tuesday and Wednesday morning will be organized by Xilinx and will be an "Embedded Design with FPGAs Workshop". Wednesday afternoon and all day Thursday will focus on the BEE2 system hardware and software architecture, hands-on experience with a BEE2 system, and the RAMP design framework. We expect attendees to participate in both parts of the workshop, as the BEE2 specific portion will follow directly from the Xilinx part. See http://www.xilinx.com/univ/uwkshp_edk.htm for more information on the Xilinx portion of the workshop.


	Agenda

	Tuesday 1/17: 9am-6pm Xilinx EDK Wednesday 1/18: 9am-12:45 Xilinx EDK Wednesday 1/18: 2:15pm-6pm BEE2 Hardware/Software Architecture Overview Thursday 1/19: 9am-12:45 BEE Hands-on Lab Thursday 1/19: 2:15pm-6pm RAMP Design Framework, RAMP Project Organization Discussion Each day will include a 1.5 hour lunch break and a 30 minute break in the morning and afternoon.


	RAMP - Jan 2006 Workshop Site Copyright ©2005-2008 Regents of the University of California. Invidial papers, presentations and textual excerpts may have other copyrights Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the NSF.