Getting Started
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Getting Started

Jan08 Retreat
Mar07 Bootcamp
Jan07 Retreat
Aug06 Workshop
Jan06 Workshop

Open System Repository

Related Research
BEE2 Project
BEE Projects

NSF Grant CNS-0551739
This material is based upon work supported by the National Science Foundation under Grant No. 0551739


Sparc International
Microsoft Research

UC Berkeley
EECS Department
CS61C Course Site
CS150 Course Site
CS152 Course Site

Getting Started with RAMP
This page is intended to be a living documentation of what you need to do to get started with the RAMP project. Some of the sections are likely to be pretty thin for a while as we build this up. Feel free to contact gdgib <at> with corrections and requets for more information.

There are several steps we recommend for anyone interested in RAMP. Much of the reading can be skimmed, especially the papers that are less interesting to you personally. Remember, RAMP is a collection of researchers and projects rather than a single system we are attempting to build.

Reading List
Over time we will work to assemble abstracts of the various RAMP and RAMP related projects here. If you are involved in RAMP and would like information about your work to appear here, email gdgib <at> a short abstract. Note that projects are listed in no particular order.

  • ProtoFlex:
    The Carnegie Mellon PROTOFLEX project is developing a simulation architecture that uses FPGAs to accelerate architectural-level full-system simulation of multiprocessors. The PROTOFLEX simulation architecture reduces the hardware complexity of simulating large multiprocessor systems by mapping many logical processors onto an interleaved multi-context execution engine. Furthermore, a hybrid simulation technique implements in the FPGA only the most frequently encountered behaviors; rare behaviors are simulated in software to more easily provide the complete set of behaviors needed in a full-system simulation. These two virtualization techniques in combination greatly reduce the efforts involved in constructing an FPGA-accelerated simulator. We have successfully applied the PROTOFLEX simulation architecture in a full-system functional simulator for a 16-way UltraSPARC III symmetric multiprocessing server. Using a single Xilinx Virtex-II XCV2P70 FPGA for acceleration, this PROTOFLEX simulator achieves an average 39x speedup (and as high 49x) over state-of-the-art software simulations for a range of benchmarking applications.

    The key members of the PROTOFLEX projects are also members of the multi-university RAMP collaboration. The PROTOFLEX developers interact closely with other RAMP PIs and students through workshops, retreats and other formal and informal meeting of the minds. The PROTOFLEX project is developed from a common baseline infrastructure with RAMP, including the FPGA emulation platform (the BEE2 and soon the BEE3) and the supporting infrastructural IPs. We expect expanded synergistic interactions with the other concurrent thrusts of the RAMP project to together address scalability, plug-and-play, timing-modeling, and other critical issues in creating an easy-to-use common facility for accelerating multiprocessor research. For more information about the PROTOFLEX project, please visit

  • HAsim:
    The HAsim project is a collaboration between MIT and Intel which focuses on using FPGAs to produce cycle-accurate performance models of microprocessors and multicore systems. Software simulators often tradeoff between simulation speed and model accuracy. At Intel, models considered to be accurate enough to guide actual design decisions typically run in the kilohertz range. By putting the model onto highly-parallel FPGAs we aim to remove these tradeoffs, resulting in accurate simulators that are also fast. Contributions of the project include developing a lightweight, distributed scheme for cycle-accurate simulations on highly-parallel environments such as FPGAs [ISFPGA], and a scheme for implementing a closely-coupled partitioned simulator on an FPGA [ISPASS]. Currently, the HAsim project has demonstrated cycle-accurate performance model of a MIPS R10K-like 4-way out-of-order superscalar core running on a Virtex 5 FPGA achieving a simulation speed of 10 MHz, a significant improvement over software-only simulators. Work is currently underway to expand this to simulating multicore-processor systems.

    Gains in simulation speed may be offset if it takes developers a long time to design the model. To that end the HAsim project has prioritized developing a common, reusable infrastructure of abstractions for FPGA programming inspired by best-practices in software engineering and high-level hardware synthesis. One of the goals of this work is to allow the programmer to develop plug-n-play modules that can be interchanged between models. On such set of plug-n-play modules is a uniform set of "virtual devices" which are mapped to the physical capabilities of a particular system, thus easing porting between different FPGA platforms. Capabilities of this system also include sharing common data types between the FPGA and software, and automatically generating circuits and code to abstract the communication, similar to the successful Remote Procedure Calls paradigm in software. In the future we hope to expand this to support more systems, such as the BEE3.

  • UT FAST & RAMP White:
    FPGA-Accelerated Simulation Technologies (FAST) is methodology for constructing simulators of complex, modern computer systems that are simultaneously accurate, fast and are capable of running real ISAs, unmodified operating systems and unmodified complex applications. Our prototype executes the x86 and PowerPC ISAs, boot Linux and Windows XP and runs applications like MySQL and Microsoft Word while modeling a complex out-of-order superscalar branch-predicted microprocessor-based system at an average speed of 1.2MIPS today and is expected to achieve 5MIPS-10MIPS in the near future.

    FAST simulators are partitioned into a functional model, that executes the functionality of the simulated system and a timing model, that predicts the performance of the simulated system. We are developing RAMP-White, a cache-coherent shared memory version of RAMP, to act as a parallel functional model to simulate parallel systems in a FAST simulator. RAMP-White is currently capable of booting an SMP operating system on top of an uncached multiprocessor based on the Leon3 processor and should soon have a coherent cache version working.

  • RAMP Gold:
    The RAMP Gold project is developing a model of a manycore processor to be used by the UC Berkeley Parallel Computing Laboratory in support of experiments in manycore architecture, operating systems, languages and runtimes, and parallel application development. The RAMP Gold target system is a single socket system with multiple processors, a configurable memory hierarchy, and a shared off-chip DRAM memory. SPARC has been chosen as the base ISA for the RAMP Gold platform, though extensive enhancements to support parallel programming are anticipated. To attain high emulator capacity and performance, the RAMP Gold emulation uses split timing and functional models, both of which are highly multithreaded. We anticipate a host platform with 8 BEE3 boards will achieve 1-10 GIPS of emulated application performance, while maintaining cycle-level timing information.