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Info |
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This matrix represents the combined knowledge of those on the RAMP project about the suitability of
various soft-core processors for use by the RAMP project. In truth it is a feature summary, and likely
to be always slightly out of date, but it has proved very helpful. The project has currently selected the
Leon3 as it's first primary target, which the Xilinx MicroBlaze being used for early development work.
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Core Selection Matrix |
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IBM |
Freescale |
Leon3 |
| ISA |
PPC405 |
PPC |
SPARC V8 |
| FPU |
No |
No (available) |
Yes (no source code) |
| Microarchitecture |
5-stage, in-order, single-issue |
7-stage, in-order? |
7-stage, in-order |
| Licensing |
Restricted |
Yes |
LGPL |
| Speed |
30MHz |
25MHz |
50MHz (0.85 MIPS/MHz) |
| Size (in 4-input LUTs, w/o FPU) |
20K |
33.5K |
8K |
| HDL |
Verilog |
Verilog |
VHDL |
| Verification Suite |
No |
No |
Yes |
| Application Base |
ok |
ok |
ok |
| OS(s) |
ok |
ok |
Linux 2.6 |
| Hardcore |
Yes |
Yes |
No |
| 64 bit |
No |
No |
No |
| SMP support |
No |
No |
Snoopy (w/o MMU) |
| Virtualizability |
No |
No |
No |
| Bus |
64-bit PLB |
64-bit AMBA AHB2.0v6 |
32-bit AMBA (64-bit soon) |
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OpenSPARC T1 (Niagara) |
ProtoFlex |
Simply RISC S1 |
| ISA |
UltraSPARC Arch 2005 (SPARC V9+) |
SPARC V9 |
UltraSPARC Arch 2005 (SPARC V9+) |
| FPU |
Yes |
Not Yet |
Yes |
| Microarchitecture |
8-core, 32-thread, 6-stage pipe (1 core/1 thread in initial FPGA version) |
ISA Only |
1-core, 4-thread derivative of OpenSPARC T1 |
| Licensing |
GPL |
SIMICS |
GPL |
| Speed |
25 MHz (Virtex-II) |
<10MIPS |
?? |
| Size (in 4-input LUTs, w/o FPU) |
135K (full 8-Core), 48K (1 thread/1 core, placed&routed) |
13K (partial core) |
?? |
| HDL |
Verilog |
Bluespec |
Verilog |
| Verification Suite |
Niagara (OpenSPARC) |
Niagara |
Niagara (OpenSPARC) |
| Application Base |
ok |
Solaris Apps |
?? |
| OS(s) |
Solaris, Linux, *BSD |
Solaris |
Solaris, Linux, *BSD |
| Hardcore |
No |
No |
No |
| 64 bit |
Yes, full 64-bit |
Yes |
Yes, full 64-bit |
| SMP support |
CMT |
Not Yet |
CMT |
| Virtualizability |
yYs (Hypervisor, LDOMs) |
No |
Yes? (via Hypervisor) |
| Bus |
128-bit |
64-bit (virtualized) |
Opencores Wishbone |
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QEMU/FAST functional |
MicroBlaze (v5.0) |
| ISA |
x86 |
MIPS-like RISC (w/o MMU) |
| FPU |
Software |
Partial IEEE 754 single precision |
| Microarchitecture |
ISA |
3-stage, in-order |
| Licensing |
LGPL |
Xilinx EDK |
| Speed |
5MIPS |
>100 MHz (0.5 MIPS/MHz) |
| Size (in 4-input LUTs, w/o FPU) |
PowerPC |
2.8K |
| HDL |
Verilog |
Encrypted VHDL |
| Verification Suite |
No |
No |
| Application Base |
Everything |
Poor |
| OS(s) |
Windows, Linux, Solaris, ... |
uClinux 2.4 |
| Hardcore |
No |
No |
| 64 bit |
Yes (speed) |
No |
| SMP support |
?? |
No |
| virtualizability |
?? |
No |
| Bus |
?? |
32-bit OPB/MCH |
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Additional Links |
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Leon3 report on Virtex-2 and Virtex-5 (section 1.3 and 1.4)
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