SCD Source recently interviewed John Wawrzynek about
the RAMP project, in particular RAMP Blue (available from the Downloads page) and the future of RAMP work at U.C. Berkeley.
We have been working to reorganize the repository, mostly to allow individual projects
more control over branching and tagging. As part of this we have drastically changed it's structure.
Please see the Repository Page for current repository access instructions and documentation.
We're starting to put together a hybrid reading list of project abstracts and set of instructions on how to become associated
with the RAMP project: the getting started page. Over the next few months we'll work
to add information to this page. In the meantime, please let us know if there's something you would like to see there.
Contact information is on the getting started page as you might expect.
We've posted a series of example template files including the BSD license, and proper headers for
use by those on the RAMP project. Over time we will try and rewrite existing files to match, but
it's unlikely that will be a priority.
Note that while the files show examples of the BSD license, they are themselves in the public domain
(as is the license itself) and may be reused with other licenses.
On Sunday, 3-2-2008 there will be a tutorial about RAMP at ASPLOS 2008.
The agenda and slides are, of course linked at left and we will be posting the slides as fast as possible.
It is long overdue, since Microsoft Research has been heavily involved of
the design of the BEE3 FPGA board which will be the platform for the next generation of RAMP systems, but we have finally
added them to the list of RAMP sponsors at left.
RAMP Blue Release
[2-25-2008]
We have now posted the first complete public release of the RAMP Blue system. Code and documentation have been posted to the
Downloads page.
RAMP Blue is the first prototype system for emulation of multi-core architectures
in FPGAs and was designed to emulate a distributed-memory
message-passing architecture. The complete system consists of 768–1008 MicroBlaze cores in 64–84 Virtex-II Pro 70 FPGAs
on 16–21 BEE2 boards, surpassing the milestone of 1000
cores in a standard 42U rack (pictures). An architecture based on point-to-point channels
and switches using a combination of custom and generic hardware provides the functionality.
Virtual-cut-through dimensional routing on one of two hybrid topologies with virtual channels provides the connectivity.
A control network with a tree topology provides management and debugging capabilities. A software infrastructure
consisting of GCC, uClinux and UPC allows running off-the-shelf applications and scientific benchmarks. Initial
performance is encouraging for emulation purposes. The full RAMP Blue paper
can be found as paper number 5 on the publications page.
New Subversion Repository
[2-21-2008]
The RAMP and BEE2 CVS repositories have been combined, and converted to Subversion (SVN). Technical details, instructions
and the procedure for getting access can be found on the repository page. We will
also be updating the BEE2 and Repository
websites to reflect these changes.
Website & Mailing List Upgrades
[1-22-2008]
We've upgraded the way the pages on this site are generated, in order to simplify maintenance of the site.
In particular we're looking to keep this site up-to-date with more detailed information about the diverse
parts of the RAMP project. In the meantime if you notice any errors or problems with the site, please
send an e-mail to Greg Gibeling (gdgib<at>berkeley.edu).
We have also done some housecleaning to set up the RAMP mailing lists a lot more logically.
If you did not receive a welcome message from the ramp-all@lists list today, please take a look at the
list of mailing lists, and let Greg Gibeling (gdgib<at>berkeley.edu)
know which ones you would like to join. For those of you who have never worked on the project or with
any of the PIs please let us know a little about yourself at the same time.